CS1 & SPI bus

Posts: 1
Joined: Wed May 27, 2015 7:45 am

CS1 & SPI bus

Wed May 27, 2015 7:55 am


I'm stuck on having the CS1 (SPI bus ) working.
I'm using a recent build of openwrt + vocore plateform.

On linux side, everything seems ok : spidev is here.
On hardware side : I've got datas and clock on the bus while I'm sending data on it.

But CS1 remains always at the high level.

Do I missing something ?

thanks for your help.


Posts: 839
Joined: Sun Oct 19, 2014 6:00 am

Re: CS1 & SPI bus

Sat May 30, 2015 12:41 am

There is a system register default make CS1 as GPIO, change this to 2b00

GPIOMODE: GPIO Purpose Select (offset: 0x0060)
Bits 22:21 RW SPI_CS1_MODE default 0x2
2’b00: SPI_CS1
2’b01: Watchdog reset output (active low for 3 system clocks)
2’b10: GPIO mode

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